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240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver.
This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based Registered DDR2 DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
* JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply * All inputs and outputs are compatible with SSTL_1.8 interface * * * * * 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) * * * * * * * * Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA 133.35 x 30.00 mm form factor Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name HYMP564R728-E3/C4 HYMP512R728-E3/C4 HYMP512R724-E3/C4 HYMP125R72M4-E3/C4 HYMP564R72P8-E3/C4 HYMP512R72P8-E3/C4 HYMP512R72P4-E3/C4 HYMP125R72MP4-E3/C4 Density 512MB 1GB 1GB 2GB 512MB 1GB 1GB 2GB Organization 64Mx72 128Mx72 128Mx72 256Mx72 64Mx72 128Mx72 128Mx72 256Mx72 # of DRAMs 9 18 18 36 9 18 18 36 # of ranks 1 2 1 2 1 2 1 2 Materials Leaded Leaded Leaded Leaded Lead free Lead free Lead free Lead free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Apr. 2005 1
1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 400 3-3-3 C4 (DDR2-533) 400 533 4-4-4 Unit Mbps Mbps Mbps tCK
ADDRESS TABLE
Density 512MB 1GB 1GB 2GB Organization Ranks 64M x 72 128M x 72 128M x 72 256M x 72 1 2 1 2 SDRAMs 64Mb x 8 64Mb x 8 128Mb x 4 128Mb x 4 # of DRAMs 9 18 18 36 # of row/bank/column Address 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms
14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms
Rev. 1.0 / Apr. 2005
2
1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description
Symbol CK0 CK0 CKE[1:0] S[1:0] ODT[1:0] RAS, CAS, WE Vref VDDQ BA[1:0] Type IN IN IN IN IN IN Supply Supply IN Polarity Positive Edge Pin Description Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Edge Active High Active Low Active High Active Low Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 On-Die Termination signals. When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Selects which DDR2 SDRAM internal bank of four is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA13) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. Positive Edge Positive line of the differential data strobe for input and output data
A[9:0], A10/AP A[13:11]
IN
-
DQ[63:0], CB[7:0] DM[8:0] VDD,VSS DQS[17:0] DQS[17:0] SA[2:0] SDA SCL VDDSPD RESET Par_In Err_Out TEST
IN IN Supply I/O I/O IN I/O IN Supply IN IN OUT
Active High
Negative Negative line of the differential data strobe for input and output data Edge These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Parity bit for the Address and Control bus("1". Odd, "0".Even) Parity error found in the Address and Control bus Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 1.0 / Apr. 2005
3
1240pin Registered DDR2 SDRAM DIMMs PIN DESCRIPTION
Pin CK0 CK0 Pin Description Clock Input,positive line Clock input,negative line Pin ODT[1:0] VDDQ Pin Description On Die Termination Inputs DQs Power Supply
CKE0~CKE1 Clock Enable Input RAS CAS WE S0,S1 A0~A9, A11~A13 A10/AP BA0,BA1 SCL SDA SA0~SA2 Par_In Err_Out RESET CB0~CB7 Row Address Strobe Column Address Strobe Write Enable Chip Select Input Address input Address input/Autoprecharge SDRAM Bank Address Serial Presence Detect(SPD) Clock Input SPD Data Input/Output E PROM Address Inputs Parity bit for the Address and Control bus Parity error found on the Address Reset Enable Data Check bit Inputs/Outputs
2
DQ0~DQ63 Data Input/Output CB0~CB7 DQS(0~8) DQS(0~8) Data check bits Input/Output Data strobes Data strobes,negative line
DM(0~8), Data Maskes/Data strobes DQS(9~17) DQS(9~17) Data strobes,negative line RFU NC TEST VDD VDDQ VSS VREF VDDSPD Reserved for Future Use No Connect Memory bus test tool (Not Connected and Not Usable on DIMMs) Core Power I/O Power Ground Input/Output Reference SPD Power
PIN LOCATION
1 pin
Front Side
64 pin 65 pin
120 pin
121 pin
Back Side
184 pin 185 pin
240 pin
Rev. 1.0 / Apr. 2005
4
1240pin Registered DDR2 SDRAM DIMMs PIN ASSIGNMENT
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Key VSS VSS VDD NC,Err_Out VDD A10/AP BA0 VDDQ WE CAS VDDQ NC, S1 NC, ODT1 VDDQ VSS DQ32 Name VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD BA2,NC NC,Err_Out VDDQ A11 A7 VDD A5 A4 VDDQ A2 VDD Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC(TEST) VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name VSS DQ4 DQ5 VSS DM0/DQS9 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 DQS10 VSS RFU RFU VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 DQS12 VSS DQ30 DQ31 VSS 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 NC= No Connect, RFU= Reserved for Future Use. Pin 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Key CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13,NC VDD VSS DQ36 DQ37 Name CB4 CB5 VSS DM8,DQS17 DQS17 VSS CB6 CB7 VSS VDDQ NC,CKE1 VDD A15,NC A14,NC VDDQ A12 A9 VDD A8 A6 VDDQ A3 A1 VDD Pin 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name VSS DM4/DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC,DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC,DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
Note: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Rev. 1.0 / Apr. 2005
5
1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx72) : HYMP564R728
/RS0
DQS0 /DQS0 DM0,DQS9 /DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
DQS4 /DQS4 DM4,DQS13 /DQS13
NU /RDQS
/CS DQS /DQS
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
NU /RDQS
/CS
DQS
/DQS
D4
DQS1 /DQS1 DM1,DQS10 /DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
DQS5 /DQS5 DM5,DQS14 /DQS14
NU /RDQS
/CS DQS /DQS
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
NU /RDQS
/CS
DQS
/DQS
D5
DQS2 /DQS2 DM2,DQS11 /DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
DQS6 /DQS6 DM6,DQS15 /DQS15
NU /RDQS
/CS DQS /DQS
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
NU /RDQS
/CS
DQS
/DQS
D6
DQS3 /DQS3 DM3,DQS12 /DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
DQS7 /DQS7 DM7,DQS16 /DQS16
NU /RDQS
/CS DQS /DQS
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
NU /RDQS
/CS
DQS
/DQS
D7
DQS8 /DQS8 DM8DQS17 /DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM RDQS I/O 0 I/O 1 I/O 2
I/O I/O I/O I/O I/O 3 4 5 6 7
Serial PD
VDD SPD
NU /RDQS
/CS DQS /DQS
Serial PD DO-D8
SCL
SCL U0
W P
SDA
SDA
VDD / VDDQ
A0
SA0
A1
SA1
A2
SA2
VREF VSS
DO-D8 DO-D8
D8
/CS0* BA0 to BA1 A0 to A13 /RAS /CAS
CKE0 /WE ODT0
R E G I S T E R
/RS0 to /CS ==> /CS: SDRAMs D0 to D8 RBA0 to RBA1 ==> BA0 to BA1: SDRAMs D0 to D8
CK0 /CK0
P L L
PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD8 /PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD8
/RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D8 /RRAS ==>/RAS: SDRAMs D0 to D8 /RCAS ==>/CAS: SDRAMs D0 to D8 RCKE0 ==> CKE: SDRAMs D0 to D8 /RWE ==> /WE: SDRAMs D0 to D8 RODT0 ==> ODT0: SDRAMs D0 to D8
/RESET
PCK7 ==> CK: Register
OE
/PCK7 ==> /CK: Register
/RESET PCK7
/RST
/PCK7
Notes : 1. Register values are 22 Ohms.
* : /S0 connects to D/CS and VDD connects to /CSR on register.
Rev. 1.0 / Apr. 2005
6
1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) : HYMP512R728
/ RS1
/ RS0
DQS0 / DQS0 DM0, DQS9 /DQS9
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 DQS / DQS
DQS4 / DQS4 DM4, DQS13 /DQS13
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 DQS / DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ1 / DQ1 DM1,DQS10 /DQS10
D0
D9
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ39
DQS5 / DQS5 DM5, DQS14 /DQS14
D4
D 13
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 / DQS2 DM 2,DQS11 /DQS11
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D1
D 10
z
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ47 DQS6 / DQS6 DM6, DQS15 /DQS15
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D5
D 14
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 / DQS3 DM3,DQS12 /DQS12
DM / CS NU RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D2
D 11
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ 55 DQS7 / DQS7 DM7, DQS16 /DQS16
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D6
D 15
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS8 / DQS8 DM8,DQS17 /DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
/S0
DM / CS NU RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D3
D 12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ 63
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D7
D 16
SCL
SCL WP Serial PD A0 SA0 A1 SA1
A1 SA2
V DD SPD
SDA
V DD /V DDQ V REF V SS
Serial PD DO-D 17 DO-D 17 DO-D 17
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS
D8
D 17
CK0 /CK0
P L L
PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D17 /PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D17
PCK7 = > CK: Register
/S1 BA0 to BA1 A0 to A13 /RAS /CAS
/WE CKE0
CKE1
1:2 R E G I S T E R
/RS0 to /CS : SDRAMs D0 - D8 /RS1 to /CS : SDRAMs D9 - D17 /RBA0 to RBA1 = > BA0 -BA1 : SDRAMs D0-D17 /RA0 to RA12 = > A0 -A12 : SDRAMs D0-D17 /RRAS = > /RAS: SDRAMs D0-D17 /RCAS = > /CAS: SDRAMs D0-D17 /RWE = > /WE: SDRAMs D0-D17 RCKE0 = > CKE0: SDRAMs D0-D8 RCKE1 = > CKE1: SDRAMs D9-D17 RODT0 = > ODT0: SDRAMs D0-D8 RODT1 = > ODT1: SDRAMs D9-D17
/RESET
OE
/PCK7 = > /CK: Register
Notes:
1. Register values are 22 Ohms +/- 5%. 2. /RS0 and /RS1 alternate between the back and front sides of the DIMM
ODT0 ODT1 /RESET PCK7
/ RST
/PCK7
Rev. 1.0 / Apr. 2005
7
1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM
1GB(64Mbx72) : HYMP512R724
VSS / RS0
/ D QS0 DQ S0 DQ0 D Q1 D Q2 D Q3 D Q S / D QS / C S I/ O0 I/O1 D0 I/O2 I/O3 DM
/ D Q S9 D Q S9 D Q4 D Q5 D Q6 D Q7 D Q S / DQ S / C S I/O0 I/O1 D9 I/O2 I/O3 DM
Serial PD
SC L
SC L U0
W P
SD A
SD A
A0
SA0
A1
SA1
A2
SA 2
/ D Q S1 D Q S1
/ D QS10 D Q S10
D Q S / DQ S / C S I/O0 I/O1 D1 I/O2 I/O3 DM
D Q8 DQ9 DQ10 D Q11
/ D Q S2 D Q S2 D Q16 D Q17 D Q18 D Q19
D Q12 DQ13 DQ14 D Q15
/ D QS11 D Q S11
D Q S / D QS / CS I/O0 I/O1 D 10 I/O2 I/O3
DM
V DD SPD V D D /V DD Q V REF
Serial PD DO-D 17 DO-D 17 DO-D 17
D Q S / DQ S / C S I/O0 I/O1 D2 I/O2 I/O3
DM
DQ20 D Q21 D Q22 DQ23
/ D QS12 D Q S12
D Q S / D QS / CS I/O0 I/O1 D 11 I/O2 I/O3
DM
V SS
/ D Q S3 D Q S3
D Q24 D Q25 D Q26 D Q27
/ D Q S4 D Q S4
D Q S / DQ S / C S I/O0 I/O1 D3 I/O2 I/O3
DM
D Q28 D Q29 D Q30 D Q31
/ D QS13 D Q S13
D Q S / D QS / CS I/O0 I/O1 D 12 I/O2 I/O3
DM
DQ32 D Q33 D Q34 DQ35
/ D Q S5 D Q S5
D Q S / DQ S / C S I/O0 I/O1 D4 I/O2 I/O3
DM
D Q36 D Q37 D Q38 D Q39
/ D QS14 D Q S14
D Q S / D QS / CS I/O0 I/O1 D 13 I/O2 I/O3
DM
D Q40 D Q41 D Q42 D Q43
/ D Q S6 D Q S6
D Q S / DQ S / C S I/O0 I/O1 D5 I/O2 I/O3
DM
DQ44 D Q45 D Q46 D Q47
/ DQ S15 D Q S15
D Q S / D QS / CS I/O0 I/O1 D 14 I/O2 I/O3
DM
D Q48 D Q49 D Q50 D Q51
/ D Q S7 D Q S7
D Q S / DQ S / C S I/O0 I/O1 D6 I/O2 I/O3
DM
D Q52 D Q53 D Q54 D Q55
/ DQ S16 D Q S16
D Q S / D QS / CS I/O0 I/O1 D 15 I/O2 I/O3
DM
D Q56 D Q57 D Q58 D Q59
/ D Q S8 D Q S8 C B0 CB1 CB2 C B3
D Q S / DQ S / C S I/O0 I/O1 D7 I/O2 I/O3
DM
DQ60 D Q61 D Q62 DQ63
/ D QS17 D Q S17
D Q S / D QS / CS I/O0 I/O1 D 16 I/O2 I/O3
DM
D Q S / DQ S / C S I/O0 I/O1 D8 I/O2 I/O3
DM
C B4 C B5 C B6 C B7
D Q S / D QS / CS I/O0 I/O1 D 17 I/O2 I/O3
DM
/C S0* BA0 to BA 1 A0 to A13 /RAS /C AS
C KE0 /W E O D T0
R E G I S T E R
CK 0
/RS0 to /C S ==> /CS: SD R AM s D 0 to D 17 R BA0 to R BA1 ==> BA0 to BA1: SD R AM s D 0 to D 17 /R A0 to R A13 ==> A0 to A13: SD R AM s D 0 to D 17 /R R AS ==>/R AS: SDR AM s D 0 to D 17 /R C AS ==>/C AS: SDR AM s D 0 to D 17 R C KE0 ==> C KE: SD RAM s D 0 to D 17 /R W E ==> /W E: SD R AM s D 0 to D 17 R O D T0 ==> O D T0: SDR AM s D 0 to D 17
/C K0
P L L
PC K 0 to PC K 6, PC K 8,PC K9 = > C K : SD R AM x D0-D17 /PC K 0 to /PC K 6, /PC K 8,/PC K9 = > /C K : SD R AM x D0-D 17
PCK 7 = > CK : R egister /R ESET
OE
/PC K7 = > /C K : Register
Notes:
1. Resistor values are 22 Ohm s +/- 5% .
/R ESET PC K7
/R ST
/PCK 7
* /S0 connects to D/CS of Register1 and /CSR of Register2. /CSR of register and D/CS of register2 connects to VDD. ** /RESET,PCK 7 connect to both Registers. Other signals connect to one of two Registers. /S1,CKE1 and ODT1 are NC.
Rev. 1.0 / Apr. 2005
8
1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) : HYMP125R72M4
VSS / RS0 / RS1
Serial PD
D QS0 / D QS0 D Q0 DQ1 DQ2 D Q3
D QS1 / D QS1 DQ8 DQ9 D Q10 D Q11
DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D1,D 19( DDP) I/O2 I/O3
D QS9 / D QS9
DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D0,D 18( DDP) I/O2 I/O3
SC L
DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D9,D 27( DDP) I/O2 I/O3
SCL
SD A U0 A0 A1 A2
SDA
D Q4 DQ5 DQ6 D Q7
DQS10 / D QS10 D Q12 D Q13 D Q14 DQ15
W P
SA 0
SA 1
SA 2
DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 10,D 28( DDP) I/O2 I/O3
V DD SPD V DD /V DDQ V REF
Serial PD DO to D 35
DO to D 35 DO to D 35
/ RS0 / RS1
D QS2 / D QS2 D Q16 DQ17 DQ18 D Q19
D QS3 / D QS3 DQ24 DQ25 DQ26 D Q27
DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D3,D 21( DDP) I/O2 I/O3
DQS11 / D QS11
DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D2,D 20( DDP) I/O2 I/O3
V SS
DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D 11,D 29( DDP) I/O2 I/O3
D Q20 D Q21 D Q22 DQ23
DQS12 / D QS12 D Q28 D Q29 D Q30 DQ31
DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 12,D 30( DDP) I/O2 I/O3
D QS8 / D QS8 C B0 CB1 CB2 C B3
DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D8,D 26( DDP) I/O2 I/O3
DQS17 / D QS17 CB4 CB5 CB6 CB7
DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 17,D 35( DDP) I/O2 I/O3
/ RS0 / RS1
D QS4 / D QS4 D Q32 DQ33 DQ34 D Q35
D QS5 / D QS5 D Q40 DQ41 DQ42 D Q43
DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D5,D 23( DDP) I/O2 I/O3
DQS13 / D QS13
DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D4,D2( DDP) I/O2 I/O3
D Q36 D Q37 D Q38 DQ39
DQS14 / D QS14 D Q44 D Q45 D Q46 DQ47
DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D 13,D 31( DDP) I/O2 I/O3
DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 14,D 32( DDP) I/O2 I/O3
/ RS0 / RS1
D QS6 / D QS6 DQ48 DQ49 DQ50 D Q51
D QS7 / D QS7 D Q56 DQ57 DQ58 D Q59
DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D7,D 25( DDP) I/O2 I/O3
DQS15 / D QS15
DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D6,D 24( DDP) I/O2 I/O3
D Q52 D Q53 D Q54 DQ55
D QS9 / D QS9 D Q60 D Q61 D Q62 DQ63
DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D 15,D 33( DDP) I/O2 I/O3
DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D9,D 34( DDP) I/O2 I/O3
/S0*
/S1* BA0 ? BA 1 A0?A13 /RAS /CAS
/W E CKE0
CKE1
1:2 R E G I S T E R
/RS0 to /CS : SDRAM s D 0 ? D 17 /RS 1 to /CS : SDRAM s D 18 ? D35 /RBA0 ? RBA1 = > BA0 -BA1 : SDRAM s D 0-D35 /RA0 ? RA 12 = > A0 -A12 : SDRAM s D 0-D 35 /RRAS = > /RAS: SDRAM s D 0-D 35 /RCAS = > /CAS: SDRAM s D 0-D35 /RW E = > /W E : SDRAM s D 0-D35 RCKE0 = > CKE 0: SDRAM s D 0-D17 RCKE 1 = > CKE1: SDRAM s D 18-D 35 RO DT0 = > O DT0: SDRAM s D 0-D17 RO DT1 = > O DT1: SDRAM s D 18-D35
/RESET PCK7 = > CK: Register /CK0 CK0
P L L
PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D35 /PCK0 to /PCK6, /PCK8,/PC K9 = > /CK : SD RAMx D0-D35
OE
/PCK7 = > /CK: Register
O DT0
ODT1 /RESET** PCK7**
/ RST
Notes:
1. Register values are 22 O hm s +/- 5% . 2. /RS 0 and /RS1 alternate between the back and front sides of the DIM M
/PCK7**
* /S0 connects to D/CS0 and /S1 connects to D/CS1 on both Registers. ** /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers.
Rev. 1.0 / Apr. 2005
9
1240pin Registered DDR2 SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VDD pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Storage Humidity(without condensation) Note : 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. Symbol VDD VDDL VDDQ VIN, VOUT TSTG HSTG Value - 1.0 V ~ 2.3 V -0.5V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -50 ~ +100 5 to 95 Unit V V V V
o
Note 1 1 1 1 1 1
C
%
OPERATING CONDITIONS
Parameter DIMM Operating temperature(ambient) DIMM Barometric Pressure(operating & storage) DRAM Component Case Temperature Range Note : 1. Up to 9850 ft. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. Symbol TOPR PBAR TCASE Rating 0 ~ +55 105 to 69 0 ~+95 Units
oC
Notes
K Pascal
o
1 2
C
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter Symbol VDD Power Supply Voltage Input Reference Voltage EEPROM Supply Voltage Termination Voltage Note : 1. 2. 3. VDDQ must be less than or equal to VDD. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) VTT of transmitting device must track VREF of receiving device. VDDL VDDQ VREF VDDSPD VTT Min 1.7 1.7 1.7 0.49 x VDDQ 1.7 VREF-0.04 Max 1.9 1.9 1.9 0.51 x VDDQ 3.6 VREF+0.04 Unit V V V V V V 3 1 2 Note
Rev. 1.0 / Apr. 2005
10
1240pin Registered DDR2 SDRAM DIMMs INPUT DC LOGIC LEVEL
Parameter Input High Voltage Input Low Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Notes
INPUT AC LOGIC LEVEL
Parameter AC Input logic High AC Input logic Low Symbol VIH(AC) VIL(AC) Min VREF + 0.250 Max VREF - 0.250 Unit V V Notes
AC INPUT TEST CONDITIONS
Symbol VREF VSWING(MAX) SLEW Notes: 1. 2. 3. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
delta TF Falling Slew = VREF - VIL(ac) max delta TF
delta TR Rising Slew = VIH(ac)min - VREF delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 1.0 / Apr. 2005
11
1240pin Registered DDR2 SDRAM DIMMs Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Note 1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Crossing point
VIX or VOX
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol VOX (ac) Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1
Rev. 1.0 / Apr. 2005
12
1240pin Registered DDR2 SDRAM DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol VOTR Notes: 1. The VDDQ of the device under test is referenced. Parameter Output Timing Measurement Reference Level SSTL_18 0.5 * VDDQ Units V Notes 1
OUTPUT DC CURRENT DRIVE
Symbol IOH(dc) IOL(dc) Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
Rev. 1.0 / Apr. 2005
13
1240pin Registered DDR2 SDRAM DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz )
512MB : HYMP564R72[P]8
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
7 8 8 8 6
11 12 12 12 9
1GB : HYMP512R72[P]8
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
7 8 10 8 8
11 12 15 12 13
1GB : HYMP512R72[P]4
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
7 8 10 8 6
11 12 15 12 9
2GB : HYMP125R72M[P]4
Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Note : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
Symbol Min Max Unit pF pF pF pF pF
CCK CI1 CI2 CI3 CIO
9.5 10.5 10.5 10.5 17
14 16 16 16 21
Rev. 1.0 / Apr. 2005
14
1240pin Registered DDR2 SDRAM DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95oC)
512MB, 64M x 72 Registered DIMM : HYMP564R72[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 E3(DDR2 400@CL 3) 1370 1460 704 965 1010 830 695 1145 1820 2000 2135 500 2630 C4(DDR2 533@CL 4) 1460 1550 713 1010 1055 875 704 1235 2090 2270 2225 500 2630 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 Notes
1GB, 128M x 72 Registered DIMM : HYMP512R72[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 E3(DDR2 400@CL3) 1865 1955 758 1280 1370 1010 740 1640 2315 2495 2630 549 3125 C4(DDR2 533@CL 4) 2045 2135 776 1370 1460 1100 758 1820 2675 2855 2810 549 3215 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 Notes
Notes : 1. IDD6 current alues are guaranted up to Tcase of 85oC max.
Rev. 1.0 / Apr. 2005 15
1240pin Registered DDR2 SDRAM DIMMs
1GB, 128M x 72 Registered DIMM : HYMP512R72[P]4
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 E3(DDR2 400@CL 3) 2090 2270 758 1280 1370 1010 740 1640 2990 2990 3620 549 4610 C4(DDR2 533@CL 4) 2270 2450 776 1370 1460 1100 758 1820 3530 3170 3800 549 4610 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
2GB, 256M x 72 Registered DIMM : HYMP125R72M[P]4
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Note : 1. IDD6 current alues are guaranted up to Tcase of 85 max. E3(DDR2 400@CL 3) 3080 3260 866 1910 2090 1370 830 2630 3980 4340 4610 648 5600 C4(DDR2 533@CL 4) 3400 3620 902 2090 2270 1550 866 2990 4700 5060 4970 648 5780 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
Rev. 1.0 / Apr. 2005
16
1240pin Registered DDR2 SDRAM DIMMs IDD Meauarement Conditions
Symbol IDD0 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0 Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1 ING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 max. Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Units mA
IDD1
mA mA mA mA mA mA mA
IDD2P IDD2Q IDD2N
IDD3P
IDD3N
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD7
mA
Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.0 / Apr. 2005
17
1240pin Registered DDR2 SDRAM DIMMs Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS DDR2-533 (C4) 4-4-4 min 4 15 15 60 45 DDR2-400 (E3) 3-3-3 min 3 15 15 55 40 tCK ns ns ns ns Unit
AC Timing Parameters by Speed Grade
Parameter Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew Clock High Level Width Clock Low Level Width Clock Half Period System Clock Cycle Time DQ and DM input setup time DQ and DM input hold time DQ and DM input setup time(single-ended strobe) DQ and DM input hold time(single-ended strobe) Control & Address input Pulse Width for each input DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tDS1 tDH1 tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE DDR2-400 Min -600 -500 0.45 0.45 min (tCL,tCH) 5000 150 275 25 25 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 Max 600 500 0.55 0.55 8000 tAC max tAC max tAC max 350 450 +0.25 0.6 DDR2-533 Min -500 -450 0.45 0.45 min (tCL,tCH) 3750 100 225 -25 -25 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 Max 500 450 0.55 0.55 8000 tAC max tAC max tAC max 300 400 +0.25 0.6 Unit Note ps ns CK CK ns ps ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK 1 1 1 1
Rev. 1.0 / Apr. 2005
18
1240pin Registered DDR2 SDRAM DIMMs
- Continued Parameter Address and control input setup time Address and control input hold time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size CAS to CAS command delay Write recovery time Auto Precharge Write Recovery + Precharge Time Write to Read Command Delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval
t
Symbol tIS tIH tRPRE tRPST tRFC tRRD tRRD tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
tCKE tAOND tAON tAONPD tAOFD tAOF
DDR2-400 Min 350 475 0.9 0.4 105 7.5 10 37.5 50 2 15 tWR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 2 Max 1.1 0.6 -
DDR2-533 Min 250 375 0.9 0.4 105 7.5 10 37.5 50 2 15 tWR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 2 2 Max 1.1 0.6 -
Unit Note ps ps tCK tCK ns ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us 2 3
AOFPD
tANPD tAXPD tOIT tDelay tREFI tREFI
tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 tAC(min)+ 2tCK+ tAC(min)+ 2tCK+ 2 tAC(max)+1 2 tAC(max)+1 2.5 2.5 2.5 2.5 tAC(max) tAC(max) tAC(min) tAC(min) + 0.6 + 0.6 tAC(min)+ 2.5tCK+tAC tAC(min)+ 2.5tCK+tAC 2 (max)+1 2 (max)+1 3 3 8 8 0 12 0 12 tIS+tCK+tI tIS+tCK+tI H H 7.8 7.8 3.9 3.9
Notes : 1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS12[4/8]21(L)F). 2. 0C TCASE 85C 3. 85C TCASE 95C
Rev. 1.0 / Apr. 2005
19
1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE
64Mx72 (1 rank) - HYMP564R72[P]8
Front
133.35
Side 2. 7 max
R E G I S T E R
( Front)
4.00.1
30.0
Detail-A
5.175
63.0
PLL
Detail-B
1. 27 0.10
5.0
55.0 5.175
Back
17.80 10.0
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
3.80
1.0
0.8 0.05
2.50
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
20
1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE
128Mx72 (2 ranks) - HYMP512R72[P]8
Front
133.35
Side
4.0 max
R E G I S T E R
4.00.1
30.0
Detail-A
5.175
63.0
PLL
Detail-B
1.27 0.10
5.0
55.0 5.175
Back
17.80 10.0
R E G I S T E R
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
2.50
1.0
0.8 0.05
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
3.80
21
1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE
128Mx72 (1 rank) - HYMP512R72[P]4
Front
133.35
Side
4.0 max
R E G I S T E R
4.00.1
30.0
Detail-A
5.175
63.0
PLL
Detail-B
1.27 0.10
5.0
55.0 5.175
Back
17.80 10.0
R E G I S T E R
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
2.50
1.0
0.8 0.05
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
3.80
22
1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE
256Mx72 (2 ranks) - HYMP125R72M[P]4
Front
133.35
Side
4. 0 max
R E G I S T E R
4.00.1
30.0
Detail-A
5.175
PLL
Detail-B
1. 27 0.10
63.0
5.0
55.0
5.175
Back
17.80 10.0
R E G I S T E R
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
3.80
1.0
0.8 0.05
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
2.50
23
1240pin Registered DDR2 SDRAM DIMMs REVISION HISTORY
Revision History First Version Release - Data sheet coverage changed from an individual module part to a component based module family. Added VDDL spec, corrected tDS & tDH spec values. Date Dec. 2004 Apr. 2005 Remark
1.0
Rev. 1.0 / Apr. 2005
24

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